UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 205

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
7.3
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
TMPn includes the following hardware.
Notes 1. TMP0, TMP2, TMP4
Remark
Configuration
f
XX
2. TMP1, TMP3, TMP5
f
XX
/128
/64
Notes 1. The TIPn0 pin functions alternately as a capture trigger input signal, external event count input
Remark
f
XX
Note 1
Note 1
: Main clock frequency
Timer register
Registers
Timer inputs
Timer outputs
Control registers
, f
, f
2. When using the functions of the TIPn0, TIPn1,TOPn0, and TOPn1 pins, see Table 4-15 Using
XX
XX
/256
/512
TIPn0
TIPn1
signal, and external trigger input signal.
Port Pin as Alternate-Function Pin.
n = 0 to 5
Item
f
f
XX
XX
f
f
f
Note 2
Note 2
XX
XX
XX
/16
/32
f
XX
/2
/4
/8
Note 2
16-bit counter
TMPn capture/compare registers 0, 1 (TPnCCR0, TPnCCR1)
TMPn counter read buffer register (TPnCNT)
CCR0, CCR1 buffer registers
2 (TIPn0
2 (TOPn0, TOPn1 pins)
TMPn control registers 0, 1 (TPnCTL0, TPnCTL1)
TMPn I/O control registers 0 to 2 (TPnIOC0 to TPnIOC2)
TMPn option register 0 (TPnOPT0)
Figure 7-1. Block Diagram of TMPn
Table 7-1. Configuration of TMPn
Note 1
, TIPn1 pins)
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP)
register
CCR0
buffer
TPnCCR0
TPnCNT
16-bit counter
Internal bus
Internal bus
Configuration
register
CCR1
TPnCCR1
buffer
Clear
INTTPnOV
INTTPnCC0
INTTPnCC1
TOPn0
TOPn1
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