UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 473

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
(n = 0 to 2)
UAnSTR
After reset: 00H
UAnOVE
The UAnTSF bit is always 1 when performing continuous transmission. When
initializing the transmission unit, check that the UAnTSF bit = 0 before performing
initialization. The transmit data is not guaranteed when initialization is performed
while the UAnTSF bit = 1.
• The operation of the UAnPE bit is controlled by the settings of the
• The UAnPE bit can be read and written, but it can only be cleared by writing 0 to it, and
• Only the first bit of the receive data stop bits is checked, regardless of the value
• The UAnFE bit can be both read and written, but it can only be cleared by
• When an overrun error occurs, the data is discarded without the next receive data
• The UAnOVE bit can be both read and written, but it can only be cleared by writing
UAnTSF
UAnTSF
UAnPE
UAnFE
UAnCTL0.UAnPS1 and UAnCTL0.UAnPS0 bits.
it cannot be set by writing 1 to it. When 1 is written to this bit, the value is retained.
of the UAnCTL0.UAnSL bit.
writing 0 to it, and it cannot be set by writing 1 to it. When 1 is written to this bit,
the value is retained.
being written to the receive buffer.
0 to it. When 1 is written to this bit, the value is retained.
<7>
0
1
0
1
0
1
0
1
• When the UAnPWR bit = 0 or the UAnTXE bit = 0 has been set.
• When, following transfer completion, there was no next data transfer
Write to UAnTX register
• When the UAnPWR bit = 0 or the UAnRXE bit = 0 has been set.
• When 0 has been written
When parity of data and parity bit do not match during reception.
• When the UAnPWR bit = 0 or the UAnRXE bit = 0 has been set
• When 0 has been written
When no stop bit is detected during reception
• When the UAnPWR bit = 0 or the UAnRXE bit = 0 has been set.
• When 0 has been written
When receive data has been set to the UAnRX register and the next
receive operation is completed before that receive data has been read
R/W
from UAnTX register
6
0
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA)
Address: UA0STR FFFFFA04H, UA1STR FFFFFA14H,
5
0
UA2STR FFFFFA24H
4
0
Transfer status flag
Overrun error flag
Framing error flag
Parity error flag
3
0
UAnPE
<2>
UAnFE
<1>
UAnOVE
<0>
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