UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 711

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
22.3 Operation
22.3.1 Reset operation via RESET pin
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
Main clock oscillator (f
Subclock oscillator (f
Internal oscillator
Peripheral clock (f
Internal system clock (f
CPU clock (f
CPU
Watchdog timer 2
Internal RAM
I/O lines (ports/alternate-function
pins)
On-chip peripheral I/O registers
Other on-chip peripheral functions
When a low level is input to the RESET pin, the system is reset, and each hardware unit is initialized.
When the level of the RESET pin is changed from low to high, the reset status is released.
Note When the power is turned on, the following pin may output an undefined level temporarily, even during reset.
Caution The OCDM register is initialized by the RESET pin input. Therefore, note with caution that, if a high
CPU
• P53/SIB2/KR3/TIQ00/TOQ00/RTP03/DDO pin
level is input to the P05/DRST pin after a reset release before the OCDM.OCDM0 bit is cleared, the on-
chip debug mode is entered. For details, see CHAPTER 4 PORT FUNCTIONS.
)
Item
X
to f
XT
X
)
X
)
CLK
/1,024)
),
Table 22-1. Hardware Status on RESET Pin Input
Oscillation stops
Oscillation continues
Oscillation stops
Operation stops
Operation stops
Initialized
Operation stops (initialized to 0)
Undefined if power-on reset or CPU access and reset input conflict (data is damaged).
Otherwise value immediately after reset input is retained.
High impedance
Initialized to specified status, OCDM register is set (01H).
Operation stops
During Reset
Note
Oscillation starts
Oscillation starts
Operation starts after securing oscillation
stabilization time
Operation starts after securing oscillation
stabilization time (initialized to fXX/8)
Program execution starts after securing
oscillation stabilization time
Counts up from 0 with internal oscillation
clock as source clock.
Operation can be started after securing
oscillation stabilization time
CHAPTER 22 RESET FUNCTIONS
After Reset
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