UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 620

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
extension codes are used here). During an INTIICn interrupt, the status is confirmed and the following steps are executed.
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
The following shows an example of the processing of the slave device by an INTIICn interrupt (it is assumed that no
<1> When a stop condition is detected, communication is terminated.
<2> When a start condition is detected, the address is confirmed. If the address does not match, communication is
<3> For data transmission/reception, when the ready flag is set, operation returns from the interrupt while the I
Remark
Interrupt servicing completed
terminated. If the address matches, the communication mode is set and wait state is released, and operation
returns from the interrupt (the ready flag is cleared).
bus remains in the wait state.
INTIICn occurred
<1> to <3> in the above correspond to <1> to <3> in Figure 17-22 Slave Operation Flowchart (2).
Set ready flag
SPDn = 1?
STDn = 1?
No
No
<3>
Yes
Yes
Figure 17-22. Slave Operation Flowchart (2)
Communication direction flag ← TRCn
<1>
<2>
Set communication mode flag
Clear ready flag
COIn = 1?
Yes
No
and communication mode flag
direction flag, ready flag,
Clear communication
CHAPTER 17 I
Page 604 of 870
2
C BUS
2
C0n