UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 756

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
(4) RESET pin
(5) Port pins (including NMI)
(6) Other signal pins
(7) Power supply
When the reset signals of the dedicated flash programmer are connected to the RESET pin that is connected to the
reset signal generator on-board, a conflict of signals occurs. To avoid the conflict of signals, isolate the connection
to the reset signal generator.
When a reset signal is input from the user system in the flash memory programming mode, the programming
operation will not be performed correctly. Therefore, do not input signals other than the reset signals from the
dedicated flash programmer.
When the system shifts to the flash memory programming mode, all the pins that are not used for flash memory
programming are in the same status as that immediately after reset. If the external device connected to each port
does not recognize the status of the port immediately after reset, pins require appropriate processing, such as
connecting to V
Connect X1, X2, XT1, XT2, and REGC in the same status as that in the normal operation mode.
During flash memory programming, input a low level to the DRST pin or leave it open. Do not input a high level.
Supply the same power (V
V850ES/JG3
DD
RESET
via a resistor or connecting to V
In the flash memory programming mode, the signal the reset signal generator
outputs conflicts with the signal the dedicated flash programmer outputs.
Therefore, isolate the signals on the reset signal generator side.
DD
, V
Figure 27-14. Conflict of Signals (RESET Pin)
SS
Conflict of signals
, EV
DD
, EV
SS
, AV
SS
REF0
Reset signal generator
via a resistor.
Dedicated flash programmer
connection pin
, AV
Output pin
REF1
, AV
SS
) as in normal operation mode.
CHAPTER 27 FLASH MEMORY
Page 740 of 870