UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 13

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

CHAPTER 18 DMA FUNCTION (DMA CONTROLLER) ................................................................... 612
CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION............................................... 635
17.8
17.9
17.10 Error Detection...................................................................................................................... 588
17.11 Extension Code..................................................................................................................... 588
17.12 Arbitration ............................................................................................................................. 589
17.13 Wakeup Function.................................................................................................................. 590
17.14 Communication Reservation............................................................................................... 591
17.15 Cautions ................................................................................................................................ 596
17.16 Communication Operations................................................................................................. 597
17.17 Timing of Data Communication .......................................................................................... 605
18.1
18.2
18.3
18.4
18.5
18.6
18.7
18.8
18.9
18.10 DMA Abort Factors ............................................................................................................... 625
18.11 End of DMA Transfer ............................................................................................................ 625
18.12 Operation Timing .................................................................................................................. 625
18.13 Cautions ................................................................................................................................ 630
19.1
19.2
19.3
19.4
17.7.4
17.7.5
17.7.6
Interrupt Request Signal (INTIICn) Generation Timing and Wait Control....................... 586
Address Match Detection Method ...................................................................................... 588
17.14.1 When communication reservation function is enabled (IICFn.IICRSVn bit = 0) .......................591
17.14.2 When communication reservation function is disabled (IICFn.IICRSVn bit = 1).......................595
17.16.1 Master operation in single master system................................................................................598
17.16.2 Master operation in multimaster system ..................................................................................599
17.16.3 Slave operation ........................................................................................................................602
Features................................................................................................................................. 612
Configuration ........................................................................................................................ 613
Registers ............................................................................................................................... 614
Transfer Targets ................................................................................................................... 621
Transfer Modes ..................................................................................................................... 622
Transfer Types ...................................................................................................................... 622
DMA Channel Priorities........................................................................................................ 623
Time Related to DMA Transfer ............................................................................................ 623
DMA Transfer Start Factors................................................................................................. 624
Features................................................................................................................................. 635
Non-Maskable Interrupts ..................................................................................................... 639
19.2.1
19.2.2
19.2.3
Maskable Interrupts.............................................................................................................. 644
19.3.1
19.3.2
19.3.3
19.3.4
19.3.5
19.3.6
19.3.7
19.3.8
Software Exception .............................................................................................................. 657
Operation without communication............................................................................................577
Arbitration loss operation (operation as slave after arbitration loss).........................................577
Operation when arbitration loss occurs (no communication after arbitration loss) ...................579
Operation .................................................................................................................................641
Restore ....................................................................................................................................642
NP flag .....................................................................................................................................643
Operation .................................................................................................................................644
Restore ....................................................................................................................................646
Priorities of maskable interrupts...............................................................................................647
Interrupt control register (xxICn) ..............................................................................................651
Interrupt mask registers 0 to 3 (IMR0 to IMR3) ........................................................................653
In-service priority register (ISPR) .............................................................................................655
ID flag ......................................................................................................................................656
Watchdog timer mode register 2 (WDTM2) .............................................................................656