UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 860

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
16-bit
timer/
event
counter
Q
(TMQ)
Function
TQ0CTL1.TQ0EEE
bit
External trigger
pulse output
mode,
one-shot pulse
output mode,
pulse width
measurement
mode
Notes on
rewriting
TQ0CCR0
register
Register setting
for operation in
external event
count mode
External event
count mode
(TQ0MD2 to
TQ0MD0 bits =
001)
TQ0IOC0.TQ0OE0,
TQ0OL0 bits
Note on
changing pulse
width during
operation
TQ0IOC0.TQ0OE0,
TQ0OL0 bits
Register setting
for operation in
one-shot pulse
output mode
Note on rewriting
TQ0CCRm
register
TQ0IC0.TQ0OE0,
TQ0OL0 bits
Capture
operation
Details of
Function
When using the external trigger pulse output mode, one-shot pulse output mode,
and pulse width measurement mode, select the internal clock as the count clock
(by clearing the TQ0CTL1.TQ0EEE bit to 0).
This bit can be set to 1 only when the interrupt request signals (INTTQ0CC0 and
INTTQ0CCk) are masked by the interrupt mask flags (TQ0CCMK0 to
TQ0CCMKk) and the timer output (TOQ0k) is performed at the same time.
However, the TQ0CCR0 and TQ0CCRk registers must be set to the same value
(see 8.5.1 (2) (d) Operation of TQ0CCR1 to TQ0CCR3 registers) (k = 1 to 3).
To change the value of the TQ0CCR0 register to a smaller value, stop counting
once and then change the set value.
If the value of the TQ0CCR0 register is rewritten to a smaller value during
counting, the 16-bit counter may overflow.
When an external clock is used as the count clock, the external clock can be
input only from the TIQ00 pin. At this time, set the TQ0IOC1.TQ0IS1 and
TQ0IOC1.TQ0IS0 bits to 00 (capture trigger input (TIQ00 pin): no edge
detection).
In the external event count mode, do not set the TQ0CCR0 register to 0000H.
In the external event count mode, use of the timer output is disabled. If
performing timer output using external event count input, set the interval timer
mode, and select the operation enabled by the external event count input for the
count clock (TQ0CTL1.TQ0MD2 to TQ0CTL1.TQ0MD0 bits = 000,
TQ0CTL1.TQ0EEE bit = 1).
Clear this bit to 0 when the TOQ00 pin is not used in the external trigger pulse
output mode.
To change the PWM waveform while the counter is operating, write the
TQ0CCR1 register last.
Rewrite the TQ0CCRk register after writing the TQ0CCR1 register after the
INTTQ0CC0 signal is detected.
Clear this bit to 0 when the TOQ00 pin is not used in the one-shot pulse output
mode.
One-shot pulses are not output even in the one-shot pulse output mode, if the
value set in the TQ0CCRk register is greater than that set in the TQ0CCR0
register.
To change the set value of the TQ0CCRm register to a smaller value, stop
counting once, and then change the set value.
If the value of the TQ0CCR0 register is rewritten to a smaller value during
counting, the 16-bit counter may overflow.
Clear this bit to 0 when the TOQ00 pin is not used in the PWM output mode.
When the capture operation is used and a slow clock is selected as the count
clock, FFFFH, not 0000H, may be captured in the TQ0CCR0, TQ0CCR1,
TQ0CCR2, and TQ0CCR3 registers if the capture trigger is input immediately
after the TQ0CE bit is set to 1.
Cautions
APPENDIX E LIST OF CAUTIONS
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