UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 542

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
16.6.13 Reception error
reception completion interrupt request signal (INTCBnR) is generated again when the next receive operation is completed
before the CBnRX register is read after the INTCBnR signal is generated, and the overrun error flag (CBnSTR.CBnOVE) is
set to 1.
reception error has occurred, the INTCBnR signal is generated again upon the next reception completion if the CBnRX
register is not read.
next receive data from the INTCBnR signal generation.
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
SIBn pin capture
When transfer is performed with reception enabled (CBnCTL0.CBnRXE bit = 1) in the continuous transfer mode, the
Even if an overrun error has occurred, the previous receive data is lost since the CBnRX register is updated. Even if a
To avoid an overrun error, complete reading the CBnRX register until one half clock before sampling the last bit of the
(1) Operation timing
INTCBnR signal
CBnRX register
CBnRX register
Shift register
CBnOVE bit
read signal
SCKBn pin
(1) Start continuous transfer.
(2) Completion of the first transfer
(3) The CBnRX register cannot be read until one half clock before the completion of the second transfer.
(4) An overrun error occurs, and the reception completion interrupt request signal (INTCBnR) is
Remark
SIBn pin
timing
generated, and then the overrun error flag (CBnSTR.CBnOVE) is set to 1. The receive data is
overwritten.
n = 0 to 4
(1)
01H
02H
05H 0AH 15H 2AH 55H AAH 00H 01H 02H 05H 0AH 15H 2AH 55H
CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB)
(2)
AAH
(3)
(4)
55H
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