UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 621

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
17.17 Timing of Data Communication
devices as its communication partner.
direction, and then starts serial communication with the slave device.
transmit data is transferred to the SO latch and is output (MSB first) via the SDA0n pin.
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
When using I
After outputting the slave address, the master device transmits the IICSn.TRCn bit, which specifies the data transfer
The shift operation of the IICn register is synchronized with the falling edge of the serial clock pin (SCL0n). The
Data input via the SDA0n pin is captured by the IICn register at the rising edge of the SCL0n pin.
The data communication timing is shown below.
Remark
n = 0 to 2
2
C bus mode, the master device outputs an address via the serial bus to select one of several slave
CHAPTER 17 I
Page 605 of 870
2
C BUS