UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 211

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
(4) TMPn I/O control register 1 (TPnIOC1)
The TPnIOC1 register is an 8-bit register that controls the valid edge of the capture trigger input signals (TIPn0,
TIPn1 pins).
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
(n = 0 to 5)
TPnIOC1
After reset: 00H
Cautions 1. Rewrite
TPnIS3
TPnIS1
0
0
1
1
0
0
1
1
7
0
2. The TPnIS3 to TPnIS0 bits are valid only in the free-
R/W
TPnIS2
TPnIS0
TPnCTL0.TPnCE bit = 0. (The same value can be written
when the TPnCE bit = 1.)
performed, clear the TPnCE bit to 0 and then set the bits
again.
running timer mode and the pulse width measurement
mode.
possible.
0
1
0
1
0
1
0
1
6
0
Address:
No edge detection (capture operation invalid)
Detection of rising edge
Detection of falling edge
Detection of both edges
No edge detection (capture operation invalid)
Detection of rising edge
Detection of falling edge
Detection of both edges
Capture trigger input signal (TIPn1 pin) valid edge setting
Capture trigger input signal (TIPn0 pin) valid edge setting
In all other modes, a capture operation is not
5
0
the
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP)
TP0IOC1 FFFFF593H, TP1IOC1 FFFFF5A3H,
TP2IOC1 FFFFF5B3H, TP3IOC1 FFFFF5C3H,
TP4IOC1 FFFFF5D3H, TP5IOC1 FFFFF5E3H
TPnIS3
4
0
TPnIS3
to
3
If rewriting was mistakenly
TPnIS0
TPnIS2
2
bits
TPnIS1
1
when
TPnIS0
0
the
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