UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 649

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
(8) Bus arbitration for CPU
(9) Registers/bits that must not be rewritten during DMA operation
(10) Be sure to set the following register bits to 0.
(11) DMA start factor
Because the DMA controller has a higher priority bus mastership than the CPU, a CPU access that takes place
during DMA transfer is held pending until the DMA transfer cycle is completed and the bus is released to the CPU.
However, the CPU can access the internal ROM, and internal RAM to/from which DMA transfer is not being
executed.
• The CPU can access the internal ROM and internal RAM when DMA transfer is being executed between the
• The CPU can access the internal ROM when DMA transfer is being executed between the on-chip peripheral I/O
Set the following registers at the following timing when a DMA operation is not under execution.
[Registers]
[Timing of setting]
• Bits 14 to 10 of DSAnH register
• Bits 14 to 10 of DDAnH register
• Bits 15, 13 to 8, and 3 to 0 of DADCn register
• Bits 6 to 3 of DCHCn register
Do not start two or more DMA channels with the same start factor. If two or more channels are started with the
same factor, DMA for which a channel has already been set may be started or a DMA channel with a lower priority
may be acknowledged earlier than a DMA channel with a higher priority. The operation cannot be guaranteed.
• DSAnH, DSAnL, DDAnH, DDAnL, DBCn, and DADCn registers
• DTFRn.IFCn5 to DTFRn.IFCn0 bits
• Period from after reset to start of the first DMA transfer
• Time after channel initialization to start of DMA transfer
• Period from after completion of DMA transfer (TCn bit = 1) to start of the next DMA transfer
external memory and on-chip peripheral I/O.
and internal RAM.
CHAPTER 18 DMA FUNCTION (DMA CONTROLLER)
Page 633 of 870