UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 318

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
(c) Notes on rewriting TQ0CCR0 register
To change the value of the TQ0CCR0 register to a smaller value, stop counting once and then change the set
value.
If the value of the TQ0CCR0 register is rewritten to a smaller value during counting, the 16-bit counter may
overflow.
Remark
If the value of the TQ0CCR0 register is changed from D
than D
rewritten. Consequently, the value of the 16-bit counter that is compared is D
Because the count value has already exceeded D
and then counts up again from 0000H. When the count value matches D
and the output of the TOQ00 pin is inverted.
Therefore, the INTTQ0CC0 signal may not be generated at the interval time “(D
“(D
Count clock period”.
2
+ 1) × Count clock cycle” originally expected, but may be generated at an interval of “(10000H + D
INTTQ0CC0 signal
1
TQ0CCR0 register
, the count value is transferred to the CCR0 buffer register as soon as the TQ0CCR0 register has been
TOQ00 pin output
Interval time (1): (D
Interval time (NG): (10000H + D
Interval time (2): (D
16-bit counter
TQ0OL0 bit
TQ0CE bit
FFFFH
0000H
L
1
2
+ 1) × Count clock cycle
+ 1) × Count clock cycle
Interval time (1)
D
2
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
1
D
+ 1) × Count clock cycle
1
2
, however, the 16-bit counter counts up to FFFFH, overflows,
D
2
Interval time (NG)
D
1
1
to D
2
while the count value is greater than D
D
2
D
2
2
, the INTTQ0CC0 signal is generated
Interval
time (2)
2
.
D
2
1
+ 1) × Count clock cycle” or
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2
but less
2
+ 1) ×