UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 35

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
2.2
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
P05/DRST
P10/ANO0, P11/ANO1
P53/DDO
AD0 to AD15
A0 to A15
A16 to A21
WAIT
CLKOUT
WR0, WR1
RD
ASTB
HLDAK
HLDRQ
Other port pins
The operation states of pins in the various modes are described below.
Notes 1. Duration until 1 ms elapses after the supply voltage reaches the operating supply voltage range (lower limit)
Remark
Pin States
Pin Name
2. Operates while alternate functions are operating.
3. In separate bus mode, the state of the pins in the idle state inserted after the T2 state is shown. In
4. Pulled down during external reset. During internal reset by the watchdog timer, clock monitor, etc., the state
5. DDO output is specified in the on-chip debug mode.
6. The bus control pins function alternately as port pins, so they are initialized to the input mode (port mode).
7. Operates even in the HALT mode, during DMA operation.
8. In separate bus mode: Hi-Z
9. In separate bus mode
when the power is turned on.
multiplexed bus mode, the state of the pins in the idle state inserted after the T3 state is shown.
of this pin differs according to the OCDM.OCDM0 bit setting.
In multiplexed bus mode: Undefined
Hi-Z: High impedance
Held: The state during the immediately preceding external bus cycle is held.
L:
H:
−:
Low-level output
High-level output
Input without sampling (not acknowledged)
When Power
Pulled down
Undefined
Is Turned
Hi-Z
On
Hi-Z
Hi-Z
Note 1
Note 6
Table 2-2. Pin Operation States in Various Modes
Power Is Turned On)
Pulled down
(Except When
During Reset
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Note 5
Note 6
Note 4
Undefined
Undefined
Operating
Notes 7, 8
Operating
Mode
HALT
H
Held
Held
Held
Held
Note 7
−
Note 2
Notes 7, 9
Note 7
Note 7
Sub-IDLE
Mode
IDLE1,
IDLE2,
Held
Held
Held
Held
Hi-Z
H
−
L
−
Note 2
Mode
CHAPTER 2 PIN FUNCTIONS
STOP
Held
Held
Held
Hi-Z
Hi-Z
H
−
L
−
Note 2
Operating
State
Held
Held
Held
Held
Held
Idle
H
−
−
Note 3
Page 19 of 870
Operating
Operating
Bus Hold
Held
Held
Held
Held
Hi-Z
Hi-Z
−
L