UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 19

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
1.2
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
Minimum instruction execution time: 31.25 ns (operating with main clock (f
General-purpose registers:
CPU features:
Memory space:
Interrupts and exceptions:
I/O lines:
Timer function:
Real-time output port:
Serial interface:
A/D converter:
D/A converter:
DMA controller:
CRC function:
DCU (debug control unit):
Clock generator:
Internal oscillation clock:
Power-save functions:
Package:
Features
• Internal memory:
• External bus interface:
32 bits × 32 registers
Signed multiplication (16 × 16 → 32): 1 to 2 clocks
Signed multiplication (32 × 32 → 64): 1 to 5 clocks
Saturated operations (overflow and underflow detection functions included)
32-bit shift instruction: 1 clock
Bit manipulation instructions
Load/store instructions with long/short format
64 MB of linear address space (for programs and data)
External expansion: Up to 16 MB (including 1 MB used as internal ROM/RAM)
Non-maskable interrupts: 2 sources
Maskable interrupts:
Software exceptions:
Exception trap:
I/O ports:
16-bit interval timer M (TMM):
16-bit timer/event counter P (TMP): 6 channels
16-bit timer/event counter Q (TMQ): 1 channel
Watch timer:
Watchdog timer:
6 bits × 1 channel
Asynchronous serial interface A (UARTA)
3-wire variable-length serial interface B (CSIB)
I
10-bit resolution: 12 channels
8-bit resolution: 2 channels
4 channels
16-bit error detection code for data in 8-bit units can be generated
JTAG interface
During main clock or subclock operation
7-level CPU clock (f
Clock-through mode/PLL mode selectable
HALT/IDLE1/IDLE2/STOP/subclock/sub-IDLE mode
100-pin plastic LQFP (fine pitch) (14 × 14)
220 kHz (TYP.)
2
C bus interface (I
UARTA/CSIB: 1 channel
UARTA/I
CSIB/I
CSIB:
RAM:
Flash memory: 384 KB/512 KB/768 KB/1024 KB (see Table 1-1)
Separate bus/multiplexed bus output selectable
8-/16-bit data bus sizing function
Wait function
Idle state function
Bus hold function
• Programmable wait function
• External wait function
2
C:
2
C:
84
2 channels
1 channel
3 channels
2
C)
XX
32 KB/40 KB/60 KB (see Table 1-1)
, f
XX
/2, f
55 sources
32 sources
2 sources
XX
/4, f
XX
1 channel
1 channel
1 channel
/8, f
XX
/16, f
XX
) of 32 MHz)
XX
/32, f
CHAPTER 1 INTRODUCTION
XT
)
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