UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 828

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
section.
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
BV
Introduction: Minimum instruction
execution time
Pin function: Pin status of
P10/ANO0, P11/ANO1 (when
power is applied)
CPU
function Internal RAM
A/D converter: Proportion of
sampling time during conversion
Reset function: Firmware operation
after releasing internal system
reset
Low-
voltage
detector
(LVI)
CRC function
Regulator: Supply clock to sub-
oscillator
Flash
memory
On-chip
debug
function
Differences between the V850ES/JG3 and V850ES/JG2 are shown below. For details, refer to each corresponding
DD
, BV
Major Differences
SS
Internal flash memory
Low-voltage detection
interrupt (INTLVI)
occurrence source
Low-voltage detection
level
RAMS.RAMF bit set
conditions
Block configuration
Boot area
Cautions on reset
related to software
breakpoint
pins
APPENDIX B MAJOR DIFFERENCES BETWEEN V850ES/JG3 AND V850ES/JG2
Table B-1. Major Differences Between V850ES/JG3 and V850ES/JG2 (1/2)
APPENDIX B MAJOR DIFFERENCES BETWEEN V850ES/JG3 AND V850ES/JG2
Changed to EV
31.25 ns
Hi-Z
384/512/768/1024 KB
32/40/60 KB
8/26 clocks
None
When supply voltage drops or rises
across the detection voltage
2.85 to 3.05 V (2.95 V (TYP.))
• Voltage lower than detection level is
• Set by instruction
Provided
Supply voltage (V
Block 0 to last block: 4 KB each
64 KB
None
detected
V850ES/JG3
DD
, EV
DD
)
SS
pins
Provided
50 ns
Undefined
128/256/384/512/640 KB
12/24/32/40/48 KB
4/26 clocks
Provided (refer to 22.3.4 (2) in User’s
Manual (U17715E))
When supply voltage drops below the
detection voltage
2.85 to 3.15 V (3.0 V (TYP.))
• Voltage lower than detection level is
• Set by instruction
• Reset by WDT2 and CLM occurs
• Reset by RESET pin occurs during
None
Regulator output voltage
Blocks 0 to 3: 28 KB each
Blocks 4 to 7: 4 KB each
Block 8 to last block: 64 KB each
56 KB
Provided (refer to 27.1.6 (3) in User’s
Manual (U17715E))
detected
internal RAM accessing
V850ES/JG2
Page 812 of 870
Throughout
2.2
3.4.4 (1)
3.4.4 (2)
13.5.2
24.3 (1)
24.3 (2)
24.3 (3)
Chapter 25
26.1
27.2
1.2
Refer to:
−
−