UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 322

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
8.5.2
TQ0CTL0.TQ0CE bit is set to 1, and an interrupt request signal (INTTQ0CC0) is generated each time the specified
number of edges have been counted. The TOQ00 pin cannot be used.
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
In the external event count mode, the valid edge of the external event count input is counted when the
Usually, the TQ0CCR1 to TQ0CCR3 registers are not used in the external event count mode.
TIQ00 pin
(external event
count input)
INTTQ0CC0 signal
TQ0CCR0 register
External event count mode (TQ0MD2 to TQ0MD0 bits = 001)
16-bit counter
TQ0CE bit
Remark
FFFFH
0000H
This figure shows the basic timing when the rising edge is specified as the valid edge of the
external event count input.
External
event
count
interval
(D
Edge
detector
0
Figure 8-9. Configuration in External Event Count Mode
Figure 8-10. Basic Timing in External Event Count Mode
D
+ 1)
0
TQ0CE bit
External
event
count
interval
(D
D
0
D
+ 1)
0
0
External
event
count
interval
(D
0
D
+ 1)
0
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
CCR0 buffer register
TQ0CCR0 register
16-bit counter
INTTQ0CC0 signal
TQ0CCR0 register
(TIQ00 pin input)
Clear
External event
16-bit counter
count input
Match signal
D
0
− 1
D
D
0
INTTQ0CC0 signal
0
0000
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