UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 852

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
Port
functions
Function
PM1 register
Port 3
P3 register
PM3 register
PMC3 register
PFC3 register
PFCE3L
register
PFC31/RXDA0
input/INTP7
input
PF3 register
Port 4
PF4 register
Port 5
Port 5 alternate
function
specifications
PF5 register
P7H register,
P7L register
PM7H register,
PM7L register
Details of
Function
When using one of the P10 and P11 pins as an I/O port and the other as a D/A
output pin, do so in an application where the port I/O level does not change during
D/A output.
The P31 to P35, P38, and P39 pins have hysteresis characteristics in the input
mode of the alternate-function pin, but do not have the hysteresis characteristics
in the port mode.
To read/write bits 8 to 15 of the P3 register in 8-bit or 1-bit units, specify them as
bits 0 to 7 of the P3H register.
To read/write bits 8 to 15 of the PM3 register in 8-bit or 1-bit units, specify them
as bits 0 to 7 of the PM3H register.
Be sure to set bits 15 to 10, 7, and 6 to “0”.
To read/write bits 8 to 15 of the PMC3 register in 8-bit or 1-bit units, specify them
as bits 0 to 7 of the PMC3H register.
To read/write bits 8 to 15 of the PFC3 register in 8-bit or 1-bit units, specify them
as bits 0 to 7 of the PFC3H register.
Be sure to set bits 7 to 3, 1, and 0 to “0”.
The INTP7 pin and RXDA0 pin are alternate-function pins. When using the pin as
the RXDA0 pin, disable edge detection for the INTP7 alternate-function pin.
(Clear the INTF3.INTF31 bit and the INTR3.INTR31 bit to 0.) When using the pin
as the INTP7 pin, stop UARTA0 reception. (Clear the UA0CTL0.UA0RXE bit to
0.)
When an output pin is pulled up at EV
To read/write bits 8 to 15 of the PF3 register in 8-bit or 1-bit units, specify them as
bits 0 to 7 of the PF3H register.
The P40 to P42 pins have hysteresis characteristics in the input mode of the
alternate-function pin, but do not have the hysteresis characteristics in the port
mode.
When an output pin is pulled up at EV
1.
The DDI, DDO, DCK, and DMS pins are used for on-chip debugging.
If on-chip debugging is not used, fix the P05/INTP2/DRST pin to low level
between when the reset signal of the RESET pin is released and when the
OCDM.OCDM0 bit is cleared (0).
For details, see 4.6.3 Cautions on on-chip debug pins.
When the power is turned on, the P53 pin may output undefined level temporarily
even during reset.
The P50 to P55 pins have hysteresis characteristics in the input mode of the
alternate function, but do not have hysteresis characteristics in the port mode.
The KRn pin and TIQ0m pin are alternate-function pins. When using the pin as
the TIQ0m pin, disable KRn pin key return detection, which is the alternate
function. (Clear the KRM.KRMn bit to 0.) Also, when using the pin as the KRn
pin, disable TIQ0m pin edge detection, which is the alternate function (n = 0 to 3,
m = 0 to 3).
When an output pin is pulled up at EV
Do not read/write the P7H and P7L registers during A/D conversion (see 13.6 (4)
Alternate I/O).
When using the P7n pin as its alternate function (ANIn pin), set the PM7n bit to 1. p. 88
Cautions
DD
DD
DD
or higher, be sure to set the PF3n bit to 1. p. 79
or higher, be sure to set the PF4n bit to
or higher, be sure to set the PF5n bit to 1. p. 86
APPENDIX E LIST OF CAUTIONS
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