UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 166

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
5.2
5.2.1
5.2.2
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
The pins used to connect an external device are listed in the table below.
When the internal ROM, internal RAM, or on-chip peripheral I/O are accessed, the status of each pin is as follows.
Caution When a write access is performed to the internal ROM area, address, data, and control signals are
For the pin status of the V850ES/JG3 in each operation mode, see 2.2 Pin States.
AD0 to AD15
A16 to A21
WAIT
CLKOUT
WR0, WR1
RD
ASTB
HLDRQ
HLDAK
AD0 to AD15
A0 to A15
A16 to A21
WAIT
CLKOUT
WR0, WR1
RD
HLDRQ
HLDAK
Address bus (A21 to A0)
Data bus (AD15 to AD0)
Control signal
Bus Control Pins
Pin status when internal ROM, internal RAM, or on-chip peripheral I/O is accessed
Pin status in each operation mode
Bus Control Pin
Bus Control Pin
Table 5-3. Pin Statuses When Internal ROM, Internal RAM, or On-Chip Peripheral I/O Is Accessed
activated in the same way as access to the external memory area.
Separate Bus Mode
PDL0 to PDL15
PDH0 to PDH5
PCM0
PCM1
PCT0, PCT1
PCT4
PCT6
PCM3
PCM2
PDL0 to PDL15
P90 to P915
PDH0 to PDH5
PCM0
PCM1
PCT0, PCT1
PCT4
PCM3
PCM2
Alternate-Function Pin
Alternate-Function Pin
Undefined
Hi-Z
Inactive
Table 5-2. External Control Pins (Separate Bus)
Table 5-1. Bus Control Pins (Multiplexed Bus)
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Input
Input
Input
Input
I/O
I/O
I/O
I/O
Address bus (A21 to A16)
Address/data bus (AD15 to AD0)
Control signal
Address/data bus
Address bus
External wait control
Internal system clock
Write strobe signal
Read strobe signal
Address strobe signal
Bus hold control
Data bus
Address bus
Address bus
External wait control
Internal system clock
Write strobe signal
Read strobe signal
Bus hold control
CHAPTER 5 BUS CONTROL FUNCTION
Multiplexed Bus Mode
Function
Function
Undefined
Undefined
Inactive
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