UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 384

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
8.5.7
set to 1. Each time the valid edge input to the TIQ0m pin has been detected, the count value of the 16-bit counter is stored
in the TQ0CCRm register, and the 16-bit counter is cleared to 0000H.
signal (INTTQ0CCm) occurs.
TQ0IOC1 register for the unused pins.
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
In the pulse width measurement mode, 16-bit timer/event counter Q starts counting when the TQ0CTL0.TQ0CE bit is
The interval of the valid edge can be measured by reading the TQ0CCRm register after a capture interrupt request
Select either of the TIQ00 to TIQ03 pins as the capture trigger input pin. Specify “No edge detected” by using the
Remark
Pulse width measurement mode (TQ0MD2 to TQ0MD0 bits = 110)
input/capture
trigger input)
trigger input)
trigger input)
trigger input)
event count
TIQ00 pin
TIQ01 pin
TIQ02 pin
TIQ03 pin
(external
(capture
(capture
(capture
m = 0 to 3
k = 1 to 3
Internal count clock
Figure 8-34. Configuration in Pulse Width Measurement Mode
detector
detector
detector
detector
detector
Edge
Edge
Edge
Edge
Edge
selection
Count
TQ0CE
clock
bit
CHAPTRER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
TQ0CCR0
(capture)
register
TQ0CCR1
(capture)
register
TQ0CCR2
(capture)
register
16-bit counter
TQ0CCR3
(capture)
register
Clear
INTTQ0OV signal
INTTQ0CC0 signal
INTTQ0CC1 signal
INTTQ0CC2 signal
INTTQ0CC3 signal
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