UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 164

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
4.6.3
high level is input to the DRST pin at this time, the on-chip debug mode is set, and the DCK, DMS, DDI, and DDO pins can
be used.
action is taken.
Handle the P05 pin with the utmost care.
4.6.4
resistor is connected. The pull-down resistor is disconnected when the OCDM0 bit is cleared (0).
4.6.5
4.6.6
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
The DRST, DCK, DMS, DDI, and DDO pins are on-chip debug pins.
After reset by the RESET pin, the P05/INTP2/DRST pin is initialized to function as an on-chip debug pin (DRST). If a
The following action must be taken if on-chip debugging is not used.
• Clear the OCDM0 bit of the OCDM register (special register) (0)
At this time, fix the P05/INTP2/DRST pin to low level from when reset by the RESET pin is released until the above
If a high level is input to the DRST pin before the above action is taken, it may cause a malfunction (CPU deadlock).
Caution After reset by the WDT2RES signal, clock monitor (CLM), or low-voltage detector (LVI), the
The P05/INTP2/DRST pin has an internal pull-down resistor (30 kΩ TYP.). After a reset by the RESET pin, a pull-down
When the power is turned on, the following pin may output an undefined level temporarily, even during reset.
• P53/SIB2/KR3/TIQ00/TOQ00/RTP03/DDO pin
In port mode, the following port pins do not have hysteresis characteristics.
P02 to P06
P31 to P35, P38, P39
P40 to P42
P50 to P55
P90 to P97, P99, P910, P912 to P915
Cautions on on-chip debug pins
Cautions on P05/INTP2/DRST pin
Cautions on P53 pin when power is turned on
Hysteresis characteristics
P05/INTP2/DRST pin is not initialized to function as an on-chip debug pin (DRST). The OCDM register
holds the current value.
CHAPTRER 4 PORT FUNCTIONS
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