UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 858

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
16-bit
timer/
event
counter P
(TMP)
16-bit
timer/
event
counter Q
(TMQ)
Function
TPnIOC0,
TPnOE0,
TPnOL0 bits
Note on
changing pulse
width during
operation
TPnIOC0.TPnOE0,
TPnOL0 bits
Register setting
for operation in
one-shot pulse
output mode
Note on
rewriting
TPnCCRm
register
TPnIOC0.TPnOE0,
TPnOL0 bits
Selector function
SELCNT0
register
Capture
operation
TQ0CTL0
register
TQ0CTL1
register
TQ0IOC0
register
Details of
Function
Clear this bit to 0 when the TOPn0 pin is not used in the external trigger pulse
output mode.
To change the PWM waveform while the counter is operating, write the TPnCCR1
register last.
Rewrite the TPnCCRm register after writing the TPnCCR1 register after the
INTTPnCC0 signal is detected.
Clear this bit to 0 when the TOPn0 pin is not used in the one-shot pulse output
mode.
One-shot pulses are not output even in the one-shot pulse output mode, if the
value set in the TPnCCR1 register is greater than that set in the TPnCCR0
register.
To change the set value of the TPnCCRm register to a smaller value, stop
counting once, and then change the set value.
If the value of the TPnCCRm register is rewritten to a smaller value during
counting, the 16-bit counter may overflow.
Clear this bit to 0 when the TOPn0 pin is not used in the PWM output mode.
When using the selector function, be sure to set the port/timer alternate function
pins for TMP to be connected to the capture trigger input.
Disable the peripheral I/Os to be connected (TMP/UARTA) before setting the
selector function.
When setting the ISEL3 or ISEL4 bit to “1”, be sure to set the corresponding
alternate-function pin to the capture trigger input.
Be sure to clear bits 7 to 5, and 2 to 0 to “0”.
When the capture operation is used and a slow clock is selected as the count
clock, FFFFH, not 0000H, may be captured in the TPnCCR0 and TPnCCR1
registers if the capture trigger is input immediately after the TPnCE bit is set to 1.
Set the TQ0CKS2 to TQ0CKS0 bits when the TQ0CE bit = 0. When the value of
the TQ0CE bit is changed from 0 to 1, the TQ0CKS2 to TQ0CKS0 bits can be set
simultaneously.
Be sure to clear bits 3 to 6 to “0”.
The TQ0EST bit is valid only in the external trigger pulse output mode or one-shot
pulse output mode. In any other mode, writing 1 to this bit is ignored.
External event count input is selected in the external event count mode regardless
of the value of the TQ0EEE bit.
Set the TQ0EEE and TQ0MD2 to TQ0MD0 bits when the TQ0CTL0.TQ0CE bit =
0. (The same value can be written when the TQ0CE bit = 1.) The operation is not
guaranteed when rewriting is performed with the TQ0CE bit = 1. If rewriting was
mistakenly performed, clear the TQ0CE bit to 0 and then set the bits again.
Be sure to clear bits 3, 4, and 7 to “0”.
Rewrite the TQ0OLm and TQ0OEm bits when the TQ0CTL0.TQ0CE bit = 0. (The
same value can be written when the TQ0CE bit = 1.) If rewriting was mistakenly
performed, clear the TQ0CE bit to 0 and then set the bits again.
Even if the TQ0OLm bit is manipulated when the TQ0CE and TQ0OEm bits are 0,
the TOQ0m pin output level varies.
Cautions
APPENDIX E LIST OF CAUTIONS
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