UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 515

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
SIBn pin capture
INTCBnR signal
(2) Operation timing
CBnTSF bit
SCKBn pin
SIBn pin
(1) Write 00H to the CBnCTL1 register, and select communication type 1, communication clock (f
(2) Write 00H to the CBnCTL2 register, and set the transfer data length to 8 bits.
(3) Write A1H to the CBnCTL0 register, and select the reception mode and MSB first at the same time as
(4) The CBnSTR.CBnTSF bit is set to 1 by performing a dummy read of the CBnRX register, and
(5) When reception is started, output the serial clock to the SCKBn pin, and capture the receive data of
(6) When reception of the transfer data length set with the CBnCTL2 register is completed, stop the serial
(7) To continue reception, read the CBnRX register with the CBnCTL0.CBnSCE bit = 1 remained after the
(8) To read the CBnRX register without starting the next reception, write the CBnSCE bit = 0.
(9) Read the CBnRX register.
(10) To end reception, write the CBnCTL0.CBnPWR bit = 0 and the CBnCTL0.CBnRXE bit = 0.
Remark
timing
f
enabling the operation of the communication clock (f
reception is started.
the SIBn pin in synchronization with the serial clock.
clock output and data capturing, generate the reception completion interrupt request signal (INTCBnR)
at the last edge of the serial clock, and clear the CBnTSF bit to 0.
INTCBnR signal is generated.
XX
/2, and master mode.
(1)
(2)
(3)
n = 0 to 4
(4)
(5)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB)
Bit 2
Bit 1
(6)
Bit 0
(7)
CCLK
Bit 7
).
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(8)
(9)
(10)
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CCLK
) =