UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 701

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
21.6 STOP Mode
21.6.1 Setting and operation status
in the normal operation mode.
CPU and the on-chip peripheral functions is stopped.
retained. The on-chip peripheral functions that operate with the clock oscillated by the subclock oscillator or an external
clock continue operating.
lower than the IDLE2 mode. If the subclock oscillator, internal oscillator, and external clock are not used, the power
consumption can be minimized with only leakage current flowing.
21.6.2 Releasing STOP mode
external interrupt request signal (INTP0 to INTP7 pin input), unmasked internal interrupt request signal from the peripheral
functions operable in the STOP mode, or reset signal (reset by RESET pin input, WDT2RES signal, or low-voltage
detector (LVI)).
has been secured.
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
The STOP mode is set by setting the PSMR.PSM1 and PSMR.PSM0 bits to 01 or 11 and setting the PSC.STP bit to 1
In the STOP mode, the subclock oscillator continues operating but the main clock oscillator stops. Clock supply to the
As a result, program execution stops, and the contents of the internal RAM before the STOP mode was set are
Table 21-9 shows the operating status in the STOP mode.
Because the STOP mode stops operation of the main clock oscillator, it reduces the power consumption to a level
Cautions 1. Insert five or more NOP instructions after the instruction that stores data in the PSC register to
The STOP mode is released by a non-maskable interrupt request signal (NMI pin input, INTWDT2 signal), unmasked
After the STOP mode has been released, the normal operation mode is restored after the oscillation stabilization time
(1) Releasing STOP mode by non-maskable interrupt request signal or unmasked maskable interrupt request
signal
The STOP mode is released by a non-maskable interrupt request signal or an unmasked maskable interrupt
request signal, regardless of the priority of the interrupt request signal. If the STOP mode is set in an interrupt
servicing routine, however, an interrupt request signal that is issued later is serviced as follows.
(a) If an interrupt request signal with a priority lower than that of the interrupt request currently being serviced is
(b) If an interrupt request signal with a priority higher than that of the interrupt request currently being serviced is
Caution The interrupt request that is disabled by setting the PSC.NMI1M, PSC.NMI0M, and PSC.INTM bits
issued, the STOP mode is released, but that interrupt request signal is not acknowledged. The interrupt
request signal itself is retained.
issued (including a non-maskable interrupt request signal), the STOP mode is released and that interrupt
request signal is acknowledged.
2. If the STOP mode is set while an unmasked interrupt request signal is being held pending, the
set the STOP mode.
STOP mode is released immediately by the pending interrupt request.
to 1 becomes invalid and STOP mode is not released.
CHAPTER 21 STANDBY FUNCTION
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