UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 862

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
Watchdog
timer 2
function
Real-time
output
function
(RTO)
Function
WDTM2 register
WDTE register
RTBL0, RTBH0
registers
RTPM0 register
RTPC0 register Set the RTPEG0, BYTE0, and EXTR0 bits only when RTPOE0 bit = 0.
Real-time
output operation
Initialization
RTBH0, RTBL0
registers
Details of
Function
If the WDTM2 register is rewritten twice after reset, an overflow signal is forcibly
generated and the counter is reset.
To intentionally generate an overflow signal, write data to the WDTM2 register
only twice, or write a value other than “ACH” to the WDTE register only once.
However, when watchdog timer 2 is set to stop operation, an overflow signal is
not generated even if data is written to the WDTM2 register only twice, or a value
other than “ACH” is written to the WDTE register only once.
To stop the operation of watchdog timer 2, set the RCM.RSTOP bit to 1 (to stop
the internal oscillator) and write 00H in the WDTM2 register. If the RCM.RSTOP
bit cannot be set to 1, set the WDCS23 bit to 1 (2
can be stopped in the IDLE1, IDLW2, sub-IDLE, and subclock operation modes).
When a value other than “ACH” is written to the WDTE register, an overflow
signal is forcibly output.
When a 1-bit memory manipulation instruction is executed for the WDTE register,
an overflow signal is forcibly output.
To intentionally generate an overflow signal, write a value other than “ACH” to the
WDTE register only once, or write data to the WDTM2 register only twice.
However, when the watchdog timer 2 is set to stop operation, an overflow signal
is not generated even if data is written to the WDTM2 register only twice, or a
value other than “ACH” is written to the WDTE register only once.
The read value of the WDTE register is “9AH” (which differs from written value
“ACH”).
When writing to bits 6 and 7 of the RTBH0 register, always write 0.
Accessing the RTBL0 and RTBH0 registers is prohibited in the following statuses.
For details, see 3.4.8 (2) Accessing specific on-chip peripheral I/O registers.
• When the CPU operates with the subclock and the main clock oscillation is
• When the CPU operates with the internal oscillation clock
After setting the real-time output port, set output data to the RTBL0 and RTBH0
registers by the time a realtime output trigger is generated.
By enabling the real-time output operation (RTPC0.RTPOE0 bit = 1), the bits
enabled to real-time output among the RTP00 to RTP05 signals perform realtime
output, and the bits set to port mode output 0.
If real-time output is disabled (RTPOE0 bit = 0), the real-time output pins (RTP00
to RTP05) all output 0, regardless of the RTPM0 register setting.
In order to use this register as the real-time output pins (RTP00 to RTP05), set
these pins as real-time output port pins using the PMC and PFC registers.
Prevent the following conflicts by software.
• Conflict between real-time output disable/enable switching (RTPOE0 bit) and
• Conflict between writing to the RTBH0 and RTBL0 registers in the real-time
Before performing initialization, disable real-time output (RTPOE0 bit = 0).
Once real-time output has been disabled (RTPOE0 bit = 0), be sure to initialize
the RTBH0 and RTBL0 registers before enabling real-time output again (RTPOE0
bit = 0 → 1).
stopped
selected real-time output trigger.
output enabled status and the selected real-time output trigger.
Cautions
n
APPENDIX E LIST OF CAUTIONS
/f
XX
is selected and the clock
Page 846 of 870
p. 396
p. 396
p. 396
p. 397
p. 397
p. 397
p. 397
p. 401
p. 401
p. 401
p. 402
p. 402
p. 402
p. 403
p. 405
p. 405
p. 405
Page
(13/36)