UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 880

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
Standby
function
Reset
function
Function
Releasing
IDLE2 mode
STOP mode
Releasing
STOP mode
Subclock
operation mode
Releasing
subclock
operation mode
Sub-IDLE mode
Releasing sub-
IDLE mode
Operating
status in sub-
IDLE mode
Emergency
operation mode
Reset function
RESF register
Hardware status
on RESET pin
input
Details of
Function
The interrupt request signal that is disabled by setting the PSC.NMI1M,
PSC.NMI0M, and PSC.INTM bits to 1 becomes invalid and IDLE2 mode is not
released.
Insert five or more NOP instructions after the instruction that stores data in the
PSC register to set the STOP mode.
If the STOP mode is set while an unmasked interrupt request signal is being held
pending, the STOP mode is released immediately by the pending interrupt
request.
The interrupt request that is disabled by setting the PSC.NMI1M, PSC.NMI0M,
and PSC.INTM bits to 1 becomes invalid and STOP mode is not released.
When manipulating the CK3 bit, do not change the set values of the PCC.CK2 to
PCC.CK0 bits (using a bit manipulation instruction to manipulate the bit is
recommended). For details of the PCC register, see 6.3 (1) Processor clock
control register (PCC).
If the following conditions are not satisfied, change the CK2 to CK0 bits so that
the conditions are satisfied and set the subclock operation mode.
Internal system clock (f
When manipulating the CK3 bit, do not change the set values of the CK2 to CK0
bits (using a bit manipulation instruction to manipulate the bit is recommended).
For details of the PCC register, see 6.3 (1) Processor clock control register
(PCC).
Be sure to stop the PLL (PLLCTL.PLLON bit = 0) before stopping the main clock.
When the CPU is operating on the subclock and main clock oscillation is stopped,
accessing a register in which a wait occurs is disabled. If a wait is generated, it
can be released only by reset (see 3.4.8 (2)).
Following the store instruction to the PSC register to set the sub-IDLE mode,
insert the five or more NOP instructions.
If the sub-IDLE mode is set while an unmasked interrupt request signal is being
held pending, the sub-IDLE mode is then released immediately by the pending
interrupt request.
The interrupt request signal that is disabled by setting the PSC.NMI1M,
PSC.NMI0M, and PSC.INTM bits to 1 becomes invalid and sub-IDLE mode is not
released.
When the sub-IDLE mode is released, 12 cycles of the subclock (about 366
elapse from when the interrupt request signal that releases the sub-IDLE mode is
generated to when the mode is released.
Be sure to stop the PLL (PLLCTL.PLLON bit = 0) before stopping the main clock.
To realize low power consumption, stop the A/D and D/A converters before
shifting to the sub-IDLE mode.
In emergency operation mode, do not access on-chip peripheral I/O registers
other than registers used for interrupts, port function, WDT2, or timer M, each of
which can operate with the internal oscillation clock. In addition, operation of
CSIB0 to CSIB4 and UARTA0 using the externally input clock is also prohibited in
this mode.
An LVI circuit internal reset does not reset the LVI circuit.
Only “0” can be written to each bit of this register. If writing “0” conflicts with
setting the flag (occurrence of reset), setting the flag takes precedence.
When the power is turned on, the following pin may output an undefined level
temporarily, even during reset.
• P53/SIB2/KR3/TIQ00/TOQ00/RTP03/DDO pin
CLK
) > Subclock (f
Cautions
XT
= 32.768 kHz) × 4
APPENDIX E LIST OF CAUTIONS
μ
s)
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