UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 856

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
Clock
generation
function
16-bit
timer/
event
counter P
(TMP)
Function
RCM register
PLLCTL
register
CKC register
LOCKR register The LOCK register does not reflect the lock status of the PLL in real time.
PLLS register
TPnCTL0
register
TPnCTL1
register
TPnIOC0
register
TPnIOC1
register
TPnIOC2
register
Details of
Function
The internal oscillator cannot be stopped while the CPU is operating on the
internal oscillation clock (CCLS.CCLSF bit = 1). Do not set the RSTOP bit to 1.
The internal oscillator oscillates if the CCLS.CCLSF bit is set to 1 (when WDT
overflow occurs during oscillation stabilization) even when the RSTOP bit is set to
1. At this time, the RSTOP bit remains being set to 1.
When the PLLON bit is cleared to 0, the SELPLL bit is automatically cleared to 0
(clockthrough mode).
The SELPLL bit can be set to 1 only when the PLL clock frequency is stabilized. If
not (unlocked), “0” is written to the SELPLL bit if data is written to it.
The PLL mode cannot be used at f
Before changing the multiplication factor between 4 and 8 by using the CKC
register, set the clock-through mode and stop the PLL.
Be sure to set bits 3 and 1 to “1” and clear bits 7 to 4 and 2 to “0”.
Set so that the lockup time is 800
Do not change the PLLS register setting during the lockup period.
Set the TPnCKS2 to TPnCKS0 bits when the TPnCE bit = 0. When the value of
the TPnCE bit is changed from 0 to 1, the TPnCKS2 to TPnCKS0 bits can be set
simultaneously.
Be sure to clear bits 3 to 6 to “0”.
The TPnEST bit is valid only in the external trigger pulse output mode or one-shot
pulse output mode. In any other mode, writing 1 to this bit is ignored.
External event count input is selected in the external event count mode regardless
of the value of the TPnEEE bit.
Set the TPnEEE and TPnMD2 to TPnMD0 bits when the TPnCTL0.TPnCE bit =
0. (The same value can be written when the TPnCE bit = 1.) The operation is not
guaranteed when rewriting is performed with the TPnCE bit = 1. If rewriting was
mistakenly performed, clear the TPnCE bit to 0 and then set the bits again.
Be sure to clear bits 3, 4, and 7 to “0”.
Rewrite the TPnOL1, TPnOE1, TPnOL0, and TPnOE0 bits when the
TPnCTL0.TPnCE bit = 0. (The same value can be written when the TPnCE bit =
1.) If rewriting was mistakenly performed, clear the TPnCE bit to 0 and then set
the bits again.
Even if the TPnOLm bit is manipulated when the TPnCE and TPnOEm bits are 0,
the TOPnm pin output level varies (m = 0, 1).
Rewrite the TPnIS3 to TPnIS0 bits when the TPnCTL0.TPnCE bit = 0. (The same
value can be written when the TPnCE bit = 1.) If rewriting was mistakenly
performed, clear the TPnCE bit to 0 and then set the bits again.
The TPnIS3 to TPnIS0 bits are valid only in the freerunning timer mode and the
pulse width measurement mode. In all other modes, a capture operation is not
possible.
Rewrite the TPnEES1, TPnEES0, TPnETS1, and TPnETS0 bits when the
TPnCTL0.TPnCE bit = 0. (The same value can be written when the TPnCE bit =
1.) If rewriting was mistakenly performed, clear the TPnCE bit to 0 and then set
the bits again.
The TPnEES1 and TPnEES0 bits are valid only when the TPnCTL1.TPnEEE bit =
1 or when the external event count mode (TPnCTL1.TPnMD2 to
TPnCTL1.TPnMD0 bits = 001) has been set.
μ
X
s or longer.
= 5.0 to 10.0 MHz.
Cautions
APPENDIX E LIST OF CAUTIONS
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