UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 487

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
15.6.8 Reception errors
result error flags are set in the UAnSTR register and a reception complete interrupt request signal (INTUAnR) is output
when an error occurs.
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
Errors during a receive operation are of three types: parity errors, framing errors, and overrun errors. Data reception
It is possible to ascertain which error occurred during reception by reading the contents of the UAnSTR register.
Clear the reception error flag by writing 0 to it after reading it.
• Receive data read flow
Caution When an INTUAnR signal is generated, the UAnSTR register must be read to check for errors.
• Reception error causes
UAnPE
UAnFE
UAnOVE
Error Flag
Parity error
Framing error
Overrun error
Reception Error
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA)
Received parity bit does not match the setting
Stop bit not detected
Reception of next data completed before data was read from receive buffer
Read UAnSTR register
Read UAnRX register
INTUAnR signal
Error processing
Error occurs?
generated?
START
END
Yes
Yes
No
No
Cause
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