UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 605

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
17.12 Arbitration
IICSn.STDn bit is set to 1), communication between the master devices is performed while the number of clocks is
adjusted until the data differs. This kind of operation is called arbitration (n = 0 to 2).
which the arbitration loss occurred, and the SCL0n and SDA0n lines are both set to high impedance, which releases the
bus (n = 0 to 2).
when a stop condition is detected, etc.) and the setting of the ALDn bit to 1, which is made by software (n = 0 to 2).
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
Transfer lines
When several master devices simultaneously generate a start condition (when the IICCn.STTn bit is set to 1 before the
When one of the master devices loses in arbitration, an arbitration loss flag (IICSn.ALDn bit) is set to 1 via the timing by
Arbitration loss is detected based on the timing of the next interrupt request signal (INTIICn) (the eighth or ninth clock,
For details of interrupt request timing, see 17.7 I
Master 1
Master 2
Remark
SDA0n
SDA0n
SDA0n
SCL0n
SCL0n
SCL0n
n = 0 to 2
Figure 17-14. Arbitration Timing Example
2
C Interrupt Request Signals (INTIICn).
Master 1 loses arbitration
CHAPTER 17 I
Hi-Z
Hi-Z
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2
C BUS