UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 317

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
(2) Interval timer mode operation timing
(a) Operation if TQ0CCR0 register is set to 0000H
(b) Operation if TQ0CCR0 register is set to FFFFH
If the TQ0CCR0 register is set to 0000H, the INTTQ0CC0 signal is generated at each count clock subsequent
to the first count clock, and the output of the TOQ00 pin is inverted.
The value of the 16-bit counter is always 0000H.
If the TQ0CCR0 register is set to FFFFH, the 16-bit counter counts up to FFFFH. The counter is cleared to
0000H in synchronization with the next count-up timing. The INTTQ0CC0 signal is generated and the output of
the TOQ00 pin is inverted. At this time, an overflow interrupt request signal (INTTQ0OV) is not generated, nor
is the overflow flag (TQ0OPT0.TQ0OVF bit) set to 1.
INTTQ0CC0 signal
TQ0CCR0 register
TOQ00 pin output
16-bit counter
Count clock
INTTQ0CC0 signal
TQ0CE bit
TQ0CCR0 register
TOQ00 pin output
16-bit counter
TQ0CE bit
FFFFH
0000H
FFFFH
count clock cycle
Interval time
10000H ×
0000H
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
count clock cycle
Interval time
10000H ×
FFFFH
0000H
0000H
count clock cycle
Count clock cycle
Interval time
Interval time
10000H ×
0000H
Count clock cycle
Interval time
0000H
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