UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 612

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
17.15 Cautions
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
(1) When IICFn.STCENn bit = 0
(2) When IICFn.STCENn bit = 1
(3) When the IICCn.IICEn bit of the V850ES/JG3 is set to 1 while communications among other devices are in
(4) Determine the operation clock frequency by the IICCLn, IICXn, and OCKSm registers before enabling the operation
(5) After the IICCn.STTn and IICCn.SPTn bits have been set to 1, they must not be re-set without being cleared to 0
(6) If transmission has been reserved, set the IICCN.SPIEn bit to 1 so that an interrupt request is generated by the detection
<1> Set the IICCLn register.
<2> Set the IICCn.IICEn bit.
<3> Set the IICCn.SPTn bit.
Immediately after the I
recognized regardless of the actual bus status. To execute master communication in the status where a stop
condition has not been detected, generate a stop condition and then release the bus before starting the master
communication.
Use the following sequence for generating a stop condition.
Immediately after I
the actual bus status. To generate the first start condition (IICCn.STTn bit = 1), it is necessary to confirm that the
bus has been released, so as to not disturb other communications.
progress, the start condition may be detected depending on the status of the communication line. Be sure to set
the IICCn.IICEn bit to 1 when the SCL0n and SDA0n lines are high level.
(IICCn.IICEn bit = 1). To change the operation clock frequency, clear the IICCn.IICEn bit to 0 once.
first.
of a stop condition.
communication data to I
condition, transmission will halt in the wait state because an interrupt request was not generated. However, it is not
necessary to set the SPIEn bit to 1 for the software to detect the IICSn.MSTSn bit.
Remark
n = 0 to 2
m = 0, 1
2
C0n operation is enabled, the bus released status (IICBSYn bit = 0) is recognized regardless of
After an interrupt request has been generated, the wait state will be released by writing
2
2
Cn, then transferring will begin. If an interrupt is not generated by the detection of a stop
C0n operation is enabled, the bus communication status (IICFn.IICBSYn bit = 1) is
CHAPTER 17 I
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C BUS