UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 857

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
16-bit
timer/
event
counter P
(TMP)
Function
TPnIOC2
register
TPnOPT0
register
TPnCCR0
register
TPnCCR1
register
TPnCNT
register
Operation
Interval timer
mode (TPnMD2
to TPnMD0 bits
= 000)
Notes on
rewriting
TPnCCR0
register
Register setting
for operation in
external event
count mode
External event
count mode
(TPnMD2 to
TPnMD0 bits =
001)
Notes on
rewriting the
TPnCCR0
register
Details of
Function
The TPnETS1 and TPnETS0 bits are valid only when the external trigger pulse
output mode (TPnCTL1.TPnMD2 to TPnCTL1.TPnMD0 bits = 010) or the one-
shot pulse output mode (TPnCTL1.TPnMD2 to TPnCTL1.TPnMD0 = 011) is set.
Rewrite the TPnCCS1 and TPnCCS0 bits when the TPnCE bit = 0. (The same
value can be written when the TPnCE bit = 1.) If rewriting was mistakenly
performed, clear the TPnCE bit to 0 and then set the bits again.
Be sure to clear bits 1 to 3, 6, and 7 to “0”.
Accessing the TPnCCR0 register is prohibited in the following statuses. For
details, see 3.4.8 (2) Accessing specific on-chip peripheral I/O registers.
• When the CPU operates with the subclock and the main clock oscillation is
• When the CPU operates with the internal oscillation clock
Accessing the TPnCCR1 register is prohibited in the following statuses. For
details, see 3.4.8 (2) Accessing specific on-chip peripheral I/O registers.
• When the CPU operates with the subclock and the main clock oscillation is
• When the CPU operates with the internal oscillation clock
Accessing the TPnCNT register is prohibited in the following statuses. For details,
see 3.4.8 (2) Accessing specific on-chip peripheral I/O registers.
• When the CPU operates with the subclock and the main clock oscillation is
• When the CPU operates with the internal oscillation clock
To use the external event count mode, specify that the valid edge of the TIPn0 pin
capture trigger input is not detected (by clearing the TPnIOC1.TPnIS1 and
TPnIOC1.TPnIS0 bits to “00”).
When using the external trigger pulse output mode, one-shot pulse output mode,
and pulse width measurement mode, select the internal clock as the count clock
(by clearing the TPnCTL1.TPnEEE bit to 0).
This bit can be set to 1 only when the interrupt request signals (INTTPnCC0 and
INTTPnCC1) are masked by the interrupt mask flags (TPnCCMK0 and
TPnCCMK1) and timer output (TOPn1) is performed at the same time. However,
set the TPnCCR0 and TPnCCR1 registers to the same value (see 7.5.1 (2) (d)
Operation of TPnCCR1 register).
To change the value of the TPnCCR0 register to a smaller value, stop counting
once and then change the set value.
If the value of the TPnCCR0 register is rewritten to a smaller value during
counting, the 16-bit counter may overflow.
When an external clock is used as the count clock, the external clock can be input
only from the TIPn0 pin. At this time, set the TPnIOC1.TPnIS1 and
TPnIOC1.TPnIS0 bits to 00 (capture trigger input (TIPn0 pin): no edge detection).
In the external event count mode, do not set the TPnCCR0 register to 0000H.
In the external event count mode, use of the timer output is disabled. If performing
timer output using external event count input, set the interval timer mode, and
select the operation enabled by the external event count input for the count clock
(TPnCTL1.TPnMD2 to TPnCTL1.TPnMD0 bits = 000, TPnCTL1.TPnEEE bit = 1).
To change the value of the TPnCCR0 register to a smaller value, stop counting
once and then change the set value.
If the value of the TPnCCR0 register is rewritten to a smaller value during
counting, the 16-bit counter may overflow.
stopped
stopped
stopped
Cautions
APPENDIX E LIST OF CAUTIONS
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