UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 198

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UPD70F3740GC-UEU-AX

Manufacturer Part Number
UPD70F3740GC-UEU-AX
Description
MCU 32BIT V850ES/JX3 100-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3r
Datasheet

Specifications of UPD70F3740GC-UEU-AX

Core Processor
RISC
Core Size
32-Bit
Speed
32MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
84
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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V850ES/JG3
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
(2) Internal oscillation mode register (RCM)
(3) CPU operation clock status register (CCLS)
Cautions 1. The internal oscillator cannot be stopped while the CPU is operating on the internal
The RCM register is an 8-bit register that sets the operation mode of the internal oscillator.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
The CCLS register indicates the status of the CPU operation clock.
This register is read-only, in 8-bit or 1-bit units.
Reset sets this register to 00H.
Note If WDT overflow occurs during oscillation stabilization after a reset is released, the CCLSF bit is set
2. The internal oscillator oscillates if the CCLS.CCLSF bit is set to 1 (when WDT overflow
to 1 and the reset value is 01H.
CCLS
After reset: 00H
RCM
After reset:
oscillation clock (CCLS.CCLSF bit = 1). Do not set the RSTOP bit to 1.
occurs during oscillation stabilization) even when the RSTOP bit is set to 1. At this time,
the RSTOP bit remains being set to 1.
RSTOP
CCLSF
00H
0
1
0
0
0
1
Note
Internal oscillator oscillation
Internal oscillator stopped
Operating on main clock (f
Operating on internal oscillation clock (f
R/W
0
0
R
Address: FFFFF80CH
Address: FFFFF82EH
0
0
Oscillation/stop of internal oscillator
CPU operation clock status
0
0
X
) or subclock (f
CHAPTER 6 CLOCK GENERATION FUNCTION
0
0
R
).
XT
).
0
0
0
0
RSTOP
CCLSF
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