UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 644

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UPD70F3740GC-UEU-AX

Manufacturer Part Number
UPD70F3740GC-UEU-AX
Description
MCU 32BIT V850ES/JX3 100-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3r
Datasheet

Specifications of UPD70F3740GC-UEU-AX

Core Processor
RISC
Core Size
32-Bit
Speed
32MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
84
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD70F3740GC-UEU-AX
Manufacturer:
NEC
Quantity:
300
Part Number:
UPD70F3740GC-UEU-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
UPD70F3740GC-UEU-AX
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
V850ES/JG3
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
Mode of processing
Notes 1. Interrupt from on-chip peripheral I/O, or software trigger (STGn bit)
Remark
DMAn transfer
System clock
DMA transfer
request
2. New DMA request of the same channel is ignored between when the first request is generated and
DFn bit
the end processing is complete.
In the case of transfer between external memory spaces (multiplexed bus, no wait)
Note 1
CPU processing
Figure 18-3. Period in Which DMA Transfer Request Is Ignored (1)
Preparation
for transfer
Read cycle
DMA0 processing
Note 2
CHAPTER 18 DMA FUNCTION (DMA CONTROLLER)
Idle
Write cycle
Note 2
processing
End
CPU processing
Note 2
Transfer request generated
after this can be acknowledged
Page 628 of 870

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