UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 721

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
(1) Operation when main clock oscillation is stopped (CLME bit = 1)
(2) Clock monitor status after RESET input
Clock monitor status
Internal oscillation
RESF.CLMRF bit
Internal oscillation
CLM.CLME bit
(CLM.CLME bit = 1 is set after RESET input and at the end of main clock oscillation stabilization time)
If oscillation of the main clock is stopped when the CLME bit = 1, an internal reset signal is generated as shown in
Figure 23-2.
RESET input clears the CLM.CLME bit to 0 and stops the clock monitor operation. When CLME bit is set to 1 by
software at the end of the oscillation stabilization time of the main clock, monitoring is started.
Internal reset
CPU operation
Main clock
Main clock
signal
RESET
clock
CLME
clock
Figure 23-2. Reset Period Due to That Oscillation of Main Clock Is Stopped
Monitoring
operation
Normal
Figure 23-3. Clock Monitor Status After RESET Input
Reset
Four internal oscillation clocks
stabilization time
Clock supply
Oscillation
stopped
Monitoring stopped
CHAPTER 23 CLOCK MONITOR
Normal operation
Set to 1 by software
Monitoring
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