UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 665

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
Caution To perform multiple interrupt servicing, the values of the EIPC and EIPSW registers must be
Interrupt request o
Interrupt request s
Interrupt request i
Interrupt request l
Figure 19-7. Example of Processing in Which Another Interrupt Request Signal Is Issued
saved before executing the EI instruction. When returning from multiple interrupt servicing,
restore the values of EIPC and EIPSW after executing the DI instruction.
(level 2)
(level 2)
(level 3)
(level 1)
Main routine
EI
Interrupt request n
request p
Interrupt request u
Interrupt
(level 2)
Interrupt request k
Interrupt
request j
(level 3)
(level 1)
(level 3)
(level 1)
request m
(level 2)
(level 2)
request t
While an Interrupt Is Being Serviced (2/2)
Interrupt
Interrupt
EI
CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION
Servicing of o
EI
request q
Interrupt
(level 1)
Servicing of s
Servicing of i
Servicing of j
Note 1
Servicing of u
Servicing of l
Servicing of n
Note 2
Servicing of t
Servicing of m
EI
Servicing of p
request r
Interrupt
(level 0)
Servicing of k
EI
Servicing of q
Pending interrupt requests t and u are
acknowledged after servicing of s.
Because the priorities of t and u are the same, u is
acknowledged first because it has the higher
default priority, regardless of the order in which the
interrupt requests have been generated.
If levels 3 to 0 are acknowledged
Interrupt request j is held pending because its
priority is lower than that of i.
k that occurs after j is acknowledged because it
has the higher priority.
Interrupt requests m and n are held pending
because servicing of l is performed in the interrupt
disabled status.
Pending interrupt requests are acknowledged after
servicing of interrupt request l.
At this time, interrupt request n is acknowledged
first even though m has occurred first because the
priority of n is higher than that of m.
Notes 1. Lower default priority
2. Higher default priority
Servicing of r
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