UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 576

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UPD70F3740GC-UEU-AX

Manufacturer Part Number
UPD70F3740GC-UEU-AX
Description
MCU 32BIT V850ES/JX3 100-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3r
Datasheet

Specifications of UPD70F3740GC-UEU-AX

Core Processor
RISC
Core Size
32-Bit
Speed
32MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
84
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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V850ES/JG3
17.6.3 Transfer direction specification
transfer direction specification bit has a value of 0, it indicates that the master device is transmitting data to a slave device.
When the transfer direction specification bit has a value of 1, it indicates that the master device is receiving data from a
slave device.
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
In addition to the 7-bit address data, the master device sends 1 bit that specifies the transfer direction. When this
Note The INTIICn signal is generated if a local address or extension code is received during slave device
Remark
operation.
n = 0 to 2
INTIICn
SDA0n
SCL0n
Figure 17-10. Transfer Direction Specification
AD6
1
AD5
2
AD4
3
AD3
4
AD2
5
AD1
Transfer direction specification
6
AD0
7
R/W
8
9
Note
CHAPTER 17 I
Page 560 of 870
2
C BUS

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