UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 231

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
each time the valid edge of external event count input is detected. Additionally, the set value of the TPnCCR0 register is
transferred to the CCR0 buffer register.
to 0000H, and a compare match interrupt request signal (INTTPnCC0) is generated.
value of TPnCCR0 register + 1) times.
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
When the TPnCE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H. The counter counts
When the count value of the 16-bit counter matches the value of the CCR0 buffer register, the 16-bit counter is cleared
The INTTPnCC0 signal is generated each time the valid edge of the external event count input has been detected (set
TPnCTL0
TPnCTL1
TPnIOC2
TPnIOC0
(a) TMPn control register 0 (TPnCTL0)
(b) TMPn control register 1 (TPnCTL1)
(c) TMPn I/O control register 0 (TPnIOC0)
(d) TMPn I/O control register 2 (TPnIOC2)
TPnCE
0/1
0
0
0
Figure 7-11. Register Setting for Operation in External Event Count Mode (1/2)
TPnEST
0
0
0
0
TPnEEE
0
0
0
0
0
0
0
0
TPnEES1
TPnOL1
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP)
0/1
0
0
0
TPnEES0 TPnETS1 TPnETS0
TPnCKS2 TPnCKS1 TPnCKS0
TPnOE1 TPnOL0
TPnMD2 TPnMD1 TPnMD0
0/1
0
0
0
0
0
0
0
TPnOE0
0
0
1
0
Select valid edge
of external event
count input
0: Disable TOPn0 pin output
0: Disable TOPn1 pin output
0, 0, 1:
External event count mode
0: Stop counting
1: Enable counting
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