UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 335

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
TQ0IOC2
(d) TMQ0 I/O control register 2 (TQ0IOC2)
(e) TMQ0 counter read buffer register (TQ0CNT)
(f) TMQ0 capture/compare registers 0 to 3 (TQ0CCR0 to TQ0CCR3)
The value of the 16-bit counter can be read by reading the TQ0CNT register.
If D
the TQ0CCR3 register, the cycle and active level of the PWM waveform are as follows.
Remarks 1. TMQ0 I/O control register 1 (TQ0IOC1) and TMQ0 option register 0 (TQ0OPT0) are not
Cycle = (D
TOQ01 pin PWM waveform active level width = D
TOQ02 pin PWM waveform active level width = D
TOQ03 pin PWM waveform active level width = D
Figure 8-18. Register Setting for Operation in External Trigger Pulse Output Mode (3/3)
0
0
is set to the TQ0CCR0 register, D
2. Updating TMQ0 capture/compare register 2 (TQ0CCR2) and TMQ0 capture/compare register
0
+ 1) × Count clock cycle
used in the external trigger pulse output mode.
3 (TQ0CCR3) is validated by writing TMQ0 capture/compare register 1 (TQ0CCR1).
0
0
0
1
TQ0EES1
to the TQ0CCR1 register, D
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
0
TQ0EES0 TQ0ETS1 TQ0ETS0
1
2
3
× Count clock cycle
× Count clock cycle
× Count clock cycle
0
0/1
2
to the TQ0CCR2 register, and D
0/1
Select valid edge of
external trigger input
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