UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 563

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
Note The TRCn bit is cleared to 0 and SDA0n line becomes high impedance when the WRELn bit is set to
Remark
Condition for clearing (COIn bit = 0)
• When a start condition is detected
• When a stop condition is detected
• Cleared by LRELn bit = 1 (communication save)
• When the IICEn bit changes from 1 to 0 (operation
• After reset
Condition for clearing (TRCn bit = 0)
• When a stop condition is detected
• Cleared by LRELn bit = 1 (communication save)
• When the IICEn bit changes from 1 to 0 (operation
• Cleared by IICCn.WRELn bit = 1
• When the ALDn bit changes from 0 to 1 (arbitration
• After reset
Master
• When “1” is output to the first byte’s LSB (transfer
Slave
• When a start condition is detected
When not used for communication
Condition for clearing (ACKDn bit = 0)
• When a stop condition is detected
• At the rising edge of the next byte’s first clock
• Cleared by LRELn bit = 1 (communication save)
• When the IICEn bit changes from 1 to 0 (operation
• After reset
ACKDn
stop)
stop)
loss)
direction specification bit)
stop)
TRCn
COIn
0
1
0
1
0
1
1 and the wait state is canceled to 0 at the ninth clock by TRCn bit = 1.
n = 0 to 2
ACK was not detected.
ACK was detected.
Addresses do not match.
Addresses match.
Receive status (other than transmit status). The SDA0n line is set to high impedance.
Transmit status. The value in the SO latch is enabled for output to the SDA0n line (valid starting at
the falling edge of the first byte’s ninth clock).
Note
Transmit/receive status detection
Matching address detection
ACK detection
Condition for setting (COIn bit = 1)
• When the received address matches the local
Condition for setting (TRCn bit = 1)
Master
• When a start condition is generated
• When “0” is output to the first byte’s LSB (transfer
Slave
• When “1” is input by the first byte’s LSB (transfer
Condition for setting (ACKDn bit = 1)
• After the SDA0n bit is set to low level at the rising
address (SVAn register) (set at the rising edge of the
eighth clock).
direction specification bit)
edge of the SCL0n pin’s ninth clock
direction specification bit)
CHAPTER 17 I
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2
C BUS
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