UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 866

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
A/D
converter
Function
Reading
ADA0CRn
register
Standby mode
High-speed
conversion
mode
A/D conversion
time
Variation of A/D
conversion
results
A/D conversion
result hysteresis
characteristics
Details of
Function
When the ADA0M0 to ADA0M2, ADA0S, ADA0PFM, or ADA0PFT register is
written, the contents of the ADA0CRn register may be undefined. Read the
conversion result after completion of conversion and before writing to the
ADA0M0 to ADA0M2, ADA0S, ADA0PFM, or ADA0PFT register. Also, when an
external/timer trigger is acknowledged, the contents of the ADA0CRn register may
be undefined. Read the conversion result after completion of conversion and
before the next external/timer trigger is acknowledged. The correct conversion
result may not be read at a timing different from the above.
Because the A/D converter stops operating in the STOP mode, conversion results
are invalid, so power consumption can be reduced. Operations are resumed after
the STOP mode is released, but the A/D conversion results after the STOP mode
is released are invalid. When using the A/D converter after the STOP mode is
released, before setting the STOP mode or releasing the STOP mode, clear the
ADA0M0.ADA0CE bit to 0 then set the ADA0CE bit to 1 after releasing the STOP
mode.
In the IDLE1, IDLE2, or subclock operation mode, operation continues. To lower
the power consumption, therefore, clear the ADA0M0.ADA0CE bit to 0. In the
IDLE1 and IDLE2 modes, since the analog input voltage value cannot be
retained, the A/D conversion results after the IDLE1 and IDLE2 modes are
released are invalid.
The results of conversions before the IDLE1 and IDLE2 modes were set are valid.
In the high-speed conversion mode, rewriting of the ADA0M0, ADA0M2, ADA0S,
ADA0PFM, and ADA0PFT registers and trigger input during the stabilization time
are prohibited.
A/D conversion time is the total time of stabilization time, conversion time, wait
time, and trigger response time (for details of these times, refer to Table 13-2
Conversion Time Selection in Normal Conversion Mode (ADA0HS1 Bit = 0)
and Table 13-3 Conversion Time Selection in High-Speed Conversion Mode
(ADA0HS1 Bit = 1)).
During A/D conversion in the normal conversion mode, if the ADA0M0, ADA0M2,
ADA0S, ADA0PFM, and ADA0PFT registers are written or a trigger is input,
reconversion is carried out. However, if the stabilization time end timing conflicts
with the writing to these registers, or if the stabilization time end timing conflicts
with the trigger input, the stabilization time of 64 clocks is reinserted.
If a conflict occurs again with the reinserted stabilization time end timing, the
stabilization time is reinserted.
Therefore do not set the trigger input interval and control register write interval to
64 clocks or below.
The results of the A/D conversion may vary depending on the fluctuation of the
supply voltage, or may be affected by noise. To reduce the variation, take
counteractive measures with the program such as averaging the A/D conversion
results.
The successive comparison type A/D converter holds the analog input voltage in
the internal sample & hold capacitor and then performs A/D conversion. After the
A/D conversion has finished, the analog input voltage remains in the internal
sample & hold capacitor. As a result, the following phenomena may occur.
• When the same channel is used for A/D conversions, if the voltage is higher or
• When switching the analog input channel, hysteresis characteristics may
lower than the previous A/D conversion, then hysteresis characteristics may
appear where the conversion result is affected by the previous value. Thus,
even if the conversion is performed at the same potential, the result may vary.
appear where the conversion result is affected by the previous channel value.
This is because one A/D converter is used for the A/D conversions. Thus, even
if the conversion is performed at the same potential, the result may vary.
Cautions
APPENDIX E LIST OF CAUTIONS
Page 850 of 870
p. 436
p. 436
p. 437
p. 437
p. 437
p. 437
Page
(17/36)