UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 694

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
21.3 HALT Mode
21.3.1 Setting and operation status
the other on-chip peripheral functions continues.
The on-chip peripheral functions that are independent of instruction processing by the CPU continue operating.
normal operation mode for intermittent operation.
21.3.2 Releasing HALT mode
external interrupt request signal (INTP0 to INTP7 pin input), unmasked internal interrupt request signal from a peripheral
function operable in the HALT mode, or reset signal (reset by RESET pin input, WDT2RES signal, low-voltage detector
(LVI), or clock monitor (CLM)).
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
Non-maskable interrupt request
signal
Maskable interrupt request signal
The HALT mode is set when a dedicated instruction (HALT) is executed in the normal operation mode.
In the HALT mode, the clock oscillator continues operating. Only clock supply to the CPU is stopped; clock supply to
As a result, program execution is stopped, and the internal RAM retains the contents before the HALT mode was set.
Table 21-3 shows the operating status in the HALT mode.
The average current consumption of the system can be reduced by using the HALT mode in combination with the
Cautions 1. Insert five or more NOP instructions after the HALT instruction.
The HALT mode is released by a non-maskable interrupt request signal (NMI pin input, INTWDT2 signal), unmasked
After the HALT mode has been released, the normal operation mode is restored.
(1) Releasing HALT mode by non-maskable interrupt request signal or unmasked maskable interrupt request
signal
The HALT mode is released by a non-maskable interrupt request signal or an unmasked maskable interrupt
request signal, regardless of the priority of the interrupt request signal. If the HALT mode is set in an interrupt
servicing routine, however, an interrupt request signal that is issued later is serviced as follows.
(a) If an interrupt request signal with a priority lower than that of the interrupt request currently being serviced is
(b) If an interrupt request signal with a priority higher than that of the interrupt request currently being serviced is
Release Source
issued, the HALT mode is released, but that interrupt request signal is not acknowledged. The interrupt
request signal itself is retained.
issued (including a non-maskable interrupt request signal), the HALT mode is released and that interrupt
request signal is acknowledged.
2. If the HALT instruction is executed while an unmasked interrupt request signal is being held
pending, the status shifts to HALT mode, but the HALT mode is then released immediately by the
pending interrupt request.
Table 21-2. Operation After Releasing HALT Mode by Interrupt Request Signal
Execution branches to the handler address.
Execution branches to the handler address
or the next instruction is executed.
Interrupt Enabled (EI) Status
The next instruction is executed.
CHAPTER 21 STANDBY FUNCTION
Interrupt Disabled (DI) Status
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