UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 414

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
11.4
operation mode and the interval time to the WDTM2 register using an 8-bit memory manipulation instruction. After this,
the operation of watchdog timer 2 cannot be stopped.
interval.
the count operation has started, write ACH to WDTE within the loop detection time interval.
maskable interrupt request signal (INTWDT2) is generated, depending on the set values of the WDM21 and
WDTM2.WDM20 bits.
reset or standby is released, no internal reset will occur and the CPU clock will switch to the internal oscillation clock.
INTWDT2 signal.
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
Watchdog timer 2 automatically starts in the reset mode following reset release.
The WDTM2 register can be written to only once following reset using byte access. To use watchdog timer 2, write the
The WDCS24 to WDCS20 bits of the WDTM2 register are used to select the watchdog timer 2 loop detection time
Writing ACH to the WDTE register clears the counter of watchdog timer 2 and starts the count operation again. After
If the time interval expires without ACH being written to the WDTE register, a reset signal (WDT2RES) or a non-
When the WDTM2.WDM21 bit is set to 1 (reset mode), if a WDT overflow occurs during oscillation stabilization after a
To not use watchdog timer 2, write 00H to the WDTM2 register.
For the non-maskable interrupt servicing while the non-maskable interrupt request mode is set, see 19.2.2 (2) From
Operation
CHAPTER 11 FUNCTIONS OF WATCHDOG TIMER 2
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