UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 201

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
(2) Clock control register (CKC)
Cautions 1. The PLL mode cannot be used at f
Remark Both the CPU clock and peripheral clock are divided by the CKC register, but only the CPU clock is
The CKC register is a special register. Data can be written to this register only in a combination of specific
sequence (see 3.4.7 Special registers).
The CKC register controls the internal system clock in the PLL mode.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 0AH.
divided by the PCC register.
2. Before changing the multiplication factor between 4 and 8 by using the CKC register, set
3. Be sure to set bits 3 and 1 to “1” and clear bits 7 to 4 and 2 to “0”.
After reset:
CKC
the clock-through mode and stop the PLL.
CKDIV0
0AH
0
1
0
f
f
XX
XX
R/W
= 4 × f
= 8 × f
0
X
X
(f
(f
Address:
Internal system clock (f
X
X
= 2.5 to 5.0 MHz)
= 2.5 to 4.0 MHz)
0
FFFFF822H
X
= 5.0 to 10.0 MHz.
0
CHAPTER 6 CLOCK GENERATION FUNCTION
XX
1
) in PLL mode
0
1
CKDIV0
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