UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 631

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
(2) DMA destination address registers 0 to 3 (DDA0 to DDA3)
Cautions 1. Be sure to clear bits 14 to 10 of the DDAnH register to 0.
The DDA0 to DDA3 registers set the DMA destination address (26 bits each) for DMA channel n (n = 0 to 3).
These registers are divided into two 16-bit registers, DDAnH and DDAnL.
These registers can be read or written in 16-bit units.
2. Set the DDAnH and DDAnL registers at the following timing when DMA transfer is disabled
3. When the value of the DDAn register is read, two 16-bit registers, DDAnH and DDAnL, are
4. Following reset, set the DSAnH, DSAnL, DDAnH, DDAnL, and DBCn registers before
(n = 0 to 3)
(n = 0 to 3)
DDAnH
DDAnL
(DCHCn.Enn bit = 0).
read. If reading and updating conflict, a value being updated may be read (see 18.13
Cautions).
starting DMA transfer. If these registers are not set, the operation when DMA transfer is
started is not guaranteed.
• Period from after reset to start of first DMA transfer
• Period from after channel initialization by DCHCn.INITn bit to start of DMA transfer
• Period from after completion of DMA transfer (DCHCn.TCn bit = 1) to start of the next
After reset: Undefined
DMA transfer
DA15 DA14 DA13 DA12
DA25 to DA16
DA15 to DA0
IR
IR
0
1
0
External memory or on-chip peripheral I/O
Internal RAM
Set an address (A25 to A16) of DMA transfer destination
(default value is undefined).
During DMA transfer, the next DMA transfer destination address is held.
When DMA transfer is completed, the DMA transfer source address set
first is held.
Set an address (A15 to A0) of DMA transfer destination
(default value is undefined).
During DMA transfer, the next DMA transfer destination address is held.
When DMA transfer is completed, the DMA transfer source address set
first is held.
0
R/W
0
DA11
0
DA10
Address: DDA0H FFFFF086H, DDA1H FFFFF08EH,
Specification of DMA transfer destination
0
CHAPTER 18 DMA FUNCTION (DMA CONTROLLER)
DA25
DA9
DA24
DDA2H FFFFF096H, DDA3H FFFFF09EH,
DDA0L FFFFF084H, DDA1L FFFFF08CH,
DDA2L FFFFF094H, DDA3L FFFFF09CH
DA8
DA23
DA7
DA22 DA21 DA20 DA19 DA18 DA17 DA16
DA6 DA5 DA4 DA3 DA2 DA1 DA0
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