UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 507

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
(2) CSIBn control register 1 (CBnCTL1)
CBnCTL1 is an 8-bit register that controls the CSIBn serial transfer operation.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
Caution The CBnCTL1 register can be rewritten only when the CBnCTL0.CBnPWR bit = 0.
(n = 0 to 4)
CBnCTL1
After reset 00H
Note Set the communication clock (f
Remark
CBnCKS2
Communication
Communication
Communication
Communication
type 1
type 2
type 3
type 4
0
0
0
0
1
1
1
1
0
R/W
CBnCKS1
When n = 0 or 1, m = 1
When n = 2 or 3, m = 2
When n = 4, m = 3
For details of f
CBnCKP
0
0
0
1
1
0
0
1
1
0
0
1
1
Address: CB0CTL1 FFFFFD01H, CB1CTL1 FFFFFD11H,
CBnCKS0
CBnDAP
CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB)
0
1
0
1
0
1
0
1
0
1
0
1
0
BRGm
CB2CTL1 FFFFFD21H, CB3CTL1 FFFFFD31H,
CB4CTL1 FFFFFD41H
SOBn
SOBn
SOBn
SOBn
SIBn capture
SIBn capture
SIBn capture
SIBn capture
SCKBn
SCKBn
SCKBn
SCKBn
, see 16.8 Baud Rate Generator.
CBnCKP CBnDAP CBnCKS2 CBnCKS1 CBnCKS0
Communication clock (f
f
f
f
f
f
f
f
External clock (SCKBn)
XX
XX
XX
XX
XX
XX
BRGm
(output)
(output)
(output)
(output)
/2
/4
/8
/16
/32
/64
(I/O)
(I/O)
(I/O)
(I/O)
CCLK
reception timing in relation to SCKBn
Specification of data transmission/
D7
D7
) to 8 MHz or lower.
D7
D7
D6
D6
D6
D6
D5
D5
CCLK
D5
D5
D4
D4
)
Note
D4
D4
D3
D3
D3
D3
Master mode
Master mode
Master mode
Master mode
Master mode
Master mode
Master mode
Slave mode
D2
D2
D2
D2
Mode
D1
D1
D1
D1
D0
D0
D0
D0
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