UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 276

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
(b) Pulse width measurement with capture register
When pulse width measurement is performed with the TPnCCRm register used as a capture register, software
processing is necessary for reading the capture register each time the INTTPnCCm signal has been detected
and for calculating an interval.
When executing pulse width measurement in the free-running timer mode, two pulse widths can be measured
with one channel.
To measure a pulse width, the pulse width can be calculated by reading the value of the TPnCCRm register in
synchronization with the INTTPnCCm signal, and calculating the difference between the read value and the
previously read value.
Remark
INTTPnCC0 signal
INTTPnCC1 signal
TPnCCR0 register
TPnCCR1 register
INTTPnOV signal
TIPn0 pin input
TIPn1 pin input
16-bit counter
TPnOVF bit
TPnCE bit
n = 0 to 5
m = 0, 1
FFFFH
0000H
Pulse interval
0000H
0000H
Pulse interval
(D
00
D
)
(D
D
00
10
10
)
Pulse interval
CHAPTRER 7 16-BIT TIMER/EVENT COUNTER P (TMP)
(10000H +
D
D
01
Cleared to 0 by
CLR instruction
Pulse interval
00
− D
(10000H +
D
D
00
11
01
)
D
− D
D
10
Pulse interval
11
10
(D
)
02
− D
D
D
Pulse interval
02
01
01
(10000H +
)
D
D
12
Cleared to 0 by
CLR instruction
11
− D
Pulse interval
(10000H +
D
D
03
11
12
D
)
− D
D
02
03
02
)
Pulse interval
(10000H +
D
13
Pulse interval
(10000H +
− D
D
04
D
D
D
12
Cleared to 0 by
CLR instruction
− D
03
12
13
)
03
)
D
04
D
D
04
13
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