UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 709

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
22.1 Overview
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
The following reset functions are available.
(1) Four kinds of reset sources
(2) Emergency operation mode
Caution An LVI circuit internal reset does not reset the LVI circuit.
Remarks 1. LVIM: Low-voltage detection register
WDT2 reset signal
CLM reset signal
• External reset input via the RESET pin
• Reset via the watchdog timer 2 (WDT2) overflow (WDT2RES)
• System reset via the comparison of the low-voltage detector (LVI) supply voltage and detected voltage
• System reset via the detecting clock monitor (CLM) oscillation stop
After a reset is released, the source of the reset can be confirmed with the reset source flag register (RESF).
If the WDT2 overflows during the main clock oscillation stabilization time inserted after reset, a main clock
oscillation anomaly is judged and the CPU starts operating on the internal oscillation clock.
Caution In emergency operation mode, do not access on-chip peripheral I/O registers other than registers
LVI reset signal
2. LVIS: Low-voltage detection level selection register
RESET
used for interrupts, port function, WDT2, or timer M, each of which can operate with the internal
oscillation clock. In addition, operation of CSIB0 to CSIB4 and UARTA0 using the externally
input clock is also prohibited in this mode.
Figure 22-1. Block Diagram of Reset Function
CHAPTER 22 RESET FUNCTIONS
WDT2RF
Set
Clear
CLMRF
Set
Clear
Reset source flag
register (RESF)
LVIRF
Set
Clear
Internal bus
CHAPTER 22 RESET FUNCTIONS
Reset signal to
LVIM/LVIS register
Reset signal
Reset signal
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