UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 169

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
5.5
5.5.1
5.5.2
can be set to 8 bits and 16 bits only.
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
Bus Cycle Type
Instruction fetch (normal access)
Instruction fetch (branch)
Operand data access
The following table shows the number of basic clocks required for accessing each resource.
Notes 1. Increases by 1 if a conflict with a data access occurs.
Remark
Each external memory area selected by memory block can be set by using the BSC register. However, the bus size
The external memory area of the V850ES/JG3 is selected by memory blocks 0 to 3.
(1) Bus size configuration register (BSC)
Bus Access
The BSC register can be read or written in 16-bit units.
Reset sets this register to 5555H.
Caution Write to the BSC register after reset, and then do not change the set values. Also, do not access
Number of clocks for access
Bus size setting function
Caution Be sure to set bits 14, 12, 10, and 8 to “1”, and clear bits 15, 13, 11, 9, 7, 5, 3, and 1 to “0”.
2. 2 + n clocks (n: Number of wait states) when the separate bus mode is selected.
Unit: Clocks/access
an external memory area until the initial settings of the BSC register are complete.
After reset:
BSC
Area (Bus Width)
BSn0
15
5555H
0
0
0
1
7
Memory block 3
8 bits
16 bits
BS30
14
1
6
R/W
Internal ROM (32 Bits)
Data bus width of CSn space (n = 0 to 3)
Address:
13
0
0
5
1
2
3
Memory block 2
BS20
FFFFF066H
12
1
4
11
0
0
3
Internal RAM (32 Bits)
Memory block 1
CHAPTER 5 BUS CONTROL FUNCTION
BS10
1
2
10
1
2
Note 1
Note 1
1
9
0
1
0
Memory block 0
External Memory (16 Bits)
BS00
1
8
0
3 + n
3 + n
3 + n
Note 2
Note 2
Note 2
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