UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 183

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
5.8.2
5.8.3
even if the HLDRQ pin is asserted.
entered. When the HLDRQ pin is later deasserted, the HLDAK pin is also deasserted, and the bus hold status is cleared.
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
The bus hold status transition procedure is shown below.
Because the internal system clock is stopped in the STOP, IDLE1, and IDLE2 modes, the bus hold status is not entered
In the HALT mode, the HLDAK pin is asserted as soon as the HLDRQ pin has been asserted, and the bus hold status is
<1> HLDRQ = 0 acknowledged
<2> All bus cycle start requests inhibited
<3> End of current bus cycle
<4> Shift to bus idle status
<5> HLDAK = 0
<6> HLDRQ = 1 acknowledged
<7> HLDAK = 1
<8> Bus cycle start request inhibition released
<9> Bus cycle starts
Bus hold procedure
Operation in power save mode
HLDAK (output)
HLDRQ (input)
<1> <2>
<3><4>
<5>
Normal status
Bus hold status
Normal status
CHAPTER 5 BUS CONTROL FUNCTION
<6>
<7><8><9>
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