UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 365

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
TOQ03 pins are inverted. When the count value of the 16-bit counter later matches the set value of the TQ0CCRm register,
a compare match interrupt request signal (INTTQ0CCm) is generated, and the output signal of the TOQ0m pin is inverted.
generates an overflow interrupt request signal (INTTQ0OV) at the next clock, is cleared to 0000H, and continues counting.
At this time, the overflow flag (TQ0OPT0.TQ0OVF bit) is also set to 1. Clear the overflow flag to 0 by executing the CLR
instruction by software.
that time, and compared with the count value.
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
When the TQ0CE bit is set to 1, 16-bit timer/event counter Q starts counting, and the output signals of the TOQ00 to
The 16-bit counter continues counting in synchronization with the count clock. When it counts up to FFFFH, it
The TQ0CCRm register can be rewritten while the counter is operating. If it is rewritten, the new value is reflected at
INTTQ0CC0 signal
INTTQ0CC1 signal
INTTQ0CC2 signal
INTTQ0CC3 signal
TQ0CCR0 register
TQ0CCR1 register
TQ0CCR2 register
TQ0CCR3 register
TOQ00 pin output
TOQ01 pin output
TOQ02 pin output
TOQ03 pin output
INTTQ0OV signal
16-bit counter
TQ0OVF bit
Figure 8-29. Basic Timing in Free-Running Timer Mode (Compare Function)
TQ0CE bit
FFFFH
0000H
D
D
10
10
D
20
D
30
D
00
D
20
Cleared to 0 by
CLR instruction
D
CHAPTRER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
30
D
D
00
11
D
20
D
30
D
00
CLR instruction
Cleared to 0 by
D
11
D
11
D
21
D
31
D
D
01
21
D
31
CLR instruction
Cleared to 0 by
D
01
D
11
D
21
D
31
D
01
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